The devices are all based on the AMRISC 2000 ASIC which is most likely an customerspecific version of RDC R8610 CPU which is a RISC CPU emulating x486.

According to the rdc.com.tw homepage it has the following specs and features:

The R8610 is a high performance and fully static 32-bit RISC microcontroller with the compatibility of Windows based, Linux and most popular 32-bit RTOS. It also integrates 16KB write direct map L1 cache, PCI rev. 2.1 32-bit bus interface at 33 MHz, SDRAM/ROM/memory controller, IPC (Internal Peripheral Controllers with DMA and interrupt timer/counter included), Fast Ethernet MAC, FIFO UART, 10/100M MAC and USB2.0 Host within a single 216-pin LQFP package to form a system-on-a-chip (SOC). It provides an ideal solution for the embedded system and communications products (such as thin client, NAT router, home gateway, access point and tablet PC) to bring about desired performance.

• Full 32-bit RISC architecture
• Supports diverse operation systems, including Windows based, Linux and most popular 32-bit RTOS
• 6-stage pipeline
• Operation frequency: 133 MHz
• Supports MMU function which includes 32 TLB entries

• Supports two-port 10/100 Fast Ethernet MAC
• IEEE 802.3u MII interface
• IEEE 802.3x flow control in full-duplex mode
• Descriptor architecture for packet TX/RX

• Provides two 8259 compatible interrupt controllers which are cascaded internally
• Independent programmable level/edge-triggered interrupt channels
• Serial IRQ supported

• Provides two 8237 DMA compatible controllers which are cascaded internally
• 4 channels for 8-bit DMA transfer and 3 channels for 16-bit transfer
• Supports 8/16/32-bit channel 4 bus master on the LPC bus

• Supports HS, FS and LS

• A high performance UART port with transmit and receive FIFOs
• Supports the programmable baud rate generator with the data rates from 50 to 115,200 bps
• The character options are programmable for 1 start bit; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8 data bits

• Supports PCI Rev 2.1 specification
• 32-bit bus interface
• Supports PCI clock at 33 MHz
• Supports PCI host
• Supports PCI master/slave
• Up to 133 Mbytes/sec maximum bandwidth
• Supports up to 3 external master devices on PCI
• Provides four PCI interrupt channels

• LPC revision 1.0 compliant
• Supports LPC/FWH (Firmware Hub) compliant interfaces
• Provides the interface to connect an LPC/FWH Flash ROM or Super I/O chip
• Supports LPC DMA
• Supports serial IRQ
• Supports bus master mode

• Provides the interface to boot ROM BIOS & DOC (Disk On Chip).
• Supports 8/16-bit data width
• Provides ROMCS_n for booting from X-bus Flash ROM
• Supports from 64K-byte to Max. 16M-byte ROM space addressing
• Supports two independent and programmable CSs (Chip Selects)

• PC100/PC133 compliant
• Supports 16-bit data bus width
• Supports speeds up to 133 MHz and above
• Supports maximum 128 MB memory space

• Unifies instructions and data cache
• Supports write through for cache write policy
• Snooping mechanism support for data coherence between main memory and cache
• Direct map

• Supports 58 programmable I/O pins
• Each GPIO pin can be individually configured to be an input/output pin

• 8254 compatible timers
• Provides three independent programmable timers / counters
• Supports a watchdog timer (WDT)
• Supports a speaker output

• Provides a direct interface to external RTC chips

The datasheet is for download here (PDF) :DataSheet